Shift Registers...
| Part Number | SN74HCS264PWR | SN74HCS264DR | SN74HCS595PWR | 74VHC9164FT | SN74HCS594PWR | SN74HCS594DYYR | SN74HCS596PWR | 74VHC164FT | SN74HC164PWR |
|---|---|---|---|---|---|---|---|---|---|
| Image |  |  |  |  | |  | |  | |
| Supplier Link | DigiKey | DigiKey | DigiKey | DigiKey | DigiKey | DigiKey | DigiKey | DigiKey | DigiKey |
| Pins | 14 | 14 | 16 | 16 | 16 | 16 | 16 | 14 | 14 |
| Package | 14-TSSOP | 14-SOIC | 16-TSSOP | 16-TSSOP | 16-TSSOP | 16-SOIC | 16-TSSOP | 14-TSSOP | 14-TSSOP |
| Pin Pitch | |||||||||
| Bits | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| Input Enable | Yes | Yes | No | No | No | No | No | Yes | Yes |
| Schmitt Inputs | Yes | Yes | Yes | Yes | Yes | Yes | Yes | No | No |
| Output Enable | No | No | Yes | No | No | No | Yes | No | No |
| Inverted Outputs | Yes | Yes | No | No | No | No | No | No | No |
| Output Storage Register | No | No | Yes | No | Yes | Yes | Yes | No | No |
| Output | Push-pull | Push-pull | Tri-state | Push-pull | Push-pull | Push-pull | Open-drain | Push-pull | Push-pull |
| Function | S to P | S to P | S to P | S to P, P to S | S to P | S to P | S to P | S to P | S to P |
| Voltage | |||||||||
| Max Current | |||||||||
| Max Frequency | |||||||||
| Clock Edge | Rising | Rising | Rising | Rising | Rising | Rising | Rising | Rising | Rising |
| Cost (for 3) | USD$1.08 | USD$1.08 | USD$1.11 | USD$1.20 | USD$1.29 | USD$1.41 | USD$1.29 | USD$1.32 | USD$1.56 |
| Remarks | Inverted output so cannot naively chain | Inverted output so cannot naively chain | Best so far |
Preferred Device
The best device seems to be the SN74HCS594PWR with its shift & storage clocks tied together—so I will move forward with this
- Adding two extra LED drivers, I realise I can improve the distribution per IC to be 7 columns per 24-channel LED driver, and 7 rows per shift register—this gives me an even distribution per IC
- This may make the shift registers more difficult to arrange (at least with an output register), as I cannot directly chain them together without skipping a row (due to the 8th bit not being used)
- This should just be a case of connecting one of the earlier parallel outputs to the input of the next shift register, but I will just need to follow the timing/clock cycles detailed in the datasheet
- This topology has an advantage of a better distribution of current per IC, making it easier to stay below the current limits
- This topology still wastes bits (55 bits), but this is better than the 87 bits of the previous arrangement—it also uses a 32 bit integer instead of a 64 bit integer, which would be preferred if the microcontroller I use has a core width of 32 bits