Current Amplifier

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As expected, we see a constant base current being sunk into the shift register when the signal is active, with a magnitude of —well within specifications.

We see that this topology is behaving as expected; sinking current through the LED when both the shift register and driver are LOW, and cutting off current when the shift register signal goes HIGH.

I am simulating with the 2SB1706 PNP transistor due to its current rating and (in the SPICE model). We see that this is capable of passing close to the desired for 105 channels, but is not quite capable of passing the full current.

Switching to the 2SB1708 with a gain and , we see the full alongside a better transient response. This tells me that this circuit should be adequate, but I do not like the high dependence on each transistor's current gain . I could use a Darlington pair topology to increase the current gain of the circuit, but I will first try a PMOS topology.

Looking at the power dissipated by the transistor, we see that it is dissipating over peak, and an average of when the row is on. This is undesirable from a PCB perspective, and also exceeds the absolute maximum power dissipation of the device (from the datasheet).

Although I could look at power transistors for better power dissipation, these will have much smaller DC gains.

As expected, we see a maximum current of to charge/discharge the gate of the FET, but zero current once the transistor is switched either on/off. This is desirable from a power dissipation perspective, as there is less current constantly being sunk/sourced by the shift registers, though I would expect the effect to be marginal due to the magnitude of the current.

Once again, we see correct behaviour of this switch, with current passing when the shift register is pulled LOW and the driver load sinking current—and current ceasing to flow once the shift register is pulled HIGH. We do observe a slower off-transition in this case however, as the gate voltage takes a few microseconds to charge back up—but this effect is negligible.

I am simulating with the IRF7205 fast switching MOSFET due to its low on resistance of , its drain current being sufficient to pass my , and its logic-level gate threshold voltage.

The low on resistance of this FET gives a power dissipation of

which should be no issue at all.

This is also verified by the simulation.

I will move forward with this design, and do a parts selection for a suitable P-Channel MOSFET, before verifying the final circuit in LTspice.